Design of modified March-C algorithm and built-in self-test architecture for memories

Resumen

Semiconductor Memories is a pivotal aspect as its technology growth increases. RAM, ROM, DRAM, etc., are the different types of memory and it becomes difficult to test the memory because of the complexity of the design increases day by day. The testing of memory is very difficult as it’s required many test patterns. In this paper, a new test architecture is designed using a response analyzer and checker to detect a fault on a chip, and the modified MARCH C algorithm is also proposed to check the fault in the memory in the shortest time.

Biografía del autor

G. Karthy, Kalasalingam Academy of research and education. Krishnankoil, (India).

B.E., M. Tech., Assistant Professor, ECE, Kalasalingam Academy of research and education. Krishnankoil, (India).

P. Sivakumar, Kalasalingam Academy of Research and Education. Krishnankoil, (India).

B.E., M.Tech., Ph.D., Professor, ECE, Kalasalingam Academy of Research and Education. Krishnankoil, (India).

Publicado
2020-03-23
Cómo citar
Karthy, G., & Sivakumar, P. (2020). Design of modified March-C algorithm and built-in self-test architecture for memories. 3C Tecnología. Glosas De Innovación Aplicadas a La Pyme, 219-229. Recuperado a partir de http://ojs.3ciencias.com/index.php/3c-tecnologia/article/view/957