Test Time Optimization by Revisiting Notes in VLSI BIST Technique

Resumen

An effective method for test time minimization in Built In Self Test (BIST) using graph theory concept with revisiting of node is incorporated in this article. Here the shortest Hamiltonian path of ISCAS89 benchmark circuit s396 is taken as an example. Minimum spanning tree with revisiting nodes is applied for s386 circuit that optimizes the time cycle for testing. Result shows that minimum spanning tree with revisiting the nodes will reduce the time cycle without compromising the test quality. Hence an effective testing is achieved using graphical approach.

Biografía del autor

H. Sribhuvaneshwari, Kalasalingam Academy of Research and Education, Krishnankoil, Tamilnadu, (India).

Research scholar, ECE Department, Kalasalingam Academy of Research and Education, Krishnankoil, Tamilnadu, (India).

K. Suthendran, Kalasalingam Academy of Research and Education, Krishnankoil, Tamilnadu, (India).

HoD/ IT Department, Kalasalingam Academy of Research and Education, Krishnankoil, Tamilnadu, (India).

Publicado
2020-03-23
Cómo citar
Sribhuvaneshwari, H., & Suthendran, K. (2020). Test Time Optimization by Revisiting Notes in VLSI BIST Technique. 3C Tecnología. Glosas De Innovación Aplicadas a La Pyme, 19-33. Recuperado a partir de http://ojs.3ciencias.com/index.php/3c-tecnologia/article/view/945